There are in fact parts that have CPUs included. However these aren’t always the best route. Sometimes you don’t want a CPU in the design at all, since software is SLOW compared to RTL designs for certain applications (DSP, Data acquisition, etc).
Xilinx has a number of SOC parts that bundle ARM cores alongside FPGA fabric, and they’re very tightly coupled to make passing data between them very efficient. These include the Zynq and Versal families.
There are already some open source cores out there, including NEORV32. There are also closed source ones, like Xilinx’s Microblaze IP. Which comes in both ARM32/64 variants, as well as RISC-V now.
There are in fact parts that have CPUs included. However these aren’t always the best route. Sometimes you don’t want a CPU in the design at all, since software is SLOW compared to RTL designs for certain applications (DSP, Data acquisition, etc).
Xilinx has a number of SOC parts that bundle ARM cores alongside FPGA fabric, and they’re very tightly coupled to make passing data between them very efficient. These include the Zynq and Versal families.
There are already some open source cores out there, including NEORV32. There are also closed source ones, like Xilinx’s Microblaze IP. Which comes in both ARM32/64 variants, as well as RISC-V now.