Its actually not seperate cores, they’re RISCV or ARM, based on a switch. MilkV does that too with one of its chips. They’re mostly the same architecturally, theres something like 10% that gets enabled/disabled with each ISA selection.
From section 3.9 Arm/RISC-V architecture switching:
There are two processor sockets on RP2350, referred to as core 0 and core 1 throughout this document. Each socket
can be occupied either by a Cortex-M33 processor (implementing the Armv8-M Main architecture, plus extensions) or by
a Hazard3 processor (implementing the RV32IMAC architecture, plus extensions).
From section 3.9.2. Mixed architecture combinations:
The ARCHSEL register has one bit for each processor socket, so it is possible to request mixed combinations of Arm
and RISC-V processors: either Arm core 0 and RISC-V core 1, or RISC-V core 0 and Arm core 1.
Practical applications for this are limited, since this requires two separate program images. The two cores interoperate
normally, including shared exclusives via the global monitor: a shared variable can be safely, concurrently accessed by
an Arm processor performing ldrex, strex instructions and a RISC-V processor performing amoadd.w instructions, for
example
Its actually not seperate cores, they’re RISCV or ARM, based on a switch. MilkV does that too with one of its chips. They’re mostly the same architecturally, theres something like 10% that gets enabled/disabled with each ISA selection.
But you can still run both at once. RP2350 datasheet
From section 3.9 Arm/RISC-V architecture switching:
From section 3.9.2. Mixed architecture combinations: