It’s really easy to come to that conclusion.

Realistically speaking a team is trying to hit a set of requirements under a set of constraints when they design a soc (or any cpu if you wanna dive into the cisc world and see the wild variation in security featureset across even the same generation of chips). That means using existing designs with a die shrink or something is often the right choice when you’re shooting for the low cost portion of the market. The technology referenced here, enhanced memory tagging extensions, is a hardware implementation of tagging that requires a specific revision of the arm design and it’s a relatively new change (mte, the precursor to emte, is flawed and not used).

So it’s not by dint of wanting to fuck you over that the designers of socs would make one without emte.